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UT54ACS164245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver Datasheet
April , 2002
FEATURES * Voltage translation - 5V bus to 3.3V bus - 3.3V bus to 5V bus * Cold sparing - 1M minimum input impedance power-off * 0.6m Commercial CMOS - Total dose: 100K rad(Si) - Single Event Latchup immune * High speed, low power consumption * Schmitt trigger inputs to filter noisy signals * Available QML Q or V processes * Standard Microcircuit Drawing 5962-98580 * Package: - 48-lead flatpack, 25 mil pitch (.390 x .640) RadHardTM DESCRIPTION The 16-bit wide UT54ACS164245S MultiPurpose transceiver is built using UTMC's Commercial epitaxial CMOS technology and is ideal for space applications. This high speed, low power UT54ACS164245S transceiver is designed to perform multiple functions including: asynchronous two-way communication, signal buffering, voltage translation, and cold sparing. With V DD equal to zero volts, the UT54ACS164245S outputs and inputs present a minimum impedance of 1M making it ideal for "cold spare" applications. Balanced outputs and low "on" output impedance make the UT54ACS164245S well suited for driving high capacitance loads and low impedance backplanes. The UT54ACS164245S enables system designers to interface 3.3 volt CMOS compatible components with 5 volt CMOS components. For voltage translation, the A port interfaces with the 3.3 volt bus; the B port interfaces with the 5 volt bus. The direction control (DIRx) controls the direction of data flow. The output enable (OEx) overrides the direction control and disables both ports. These signals can be driven from either port A or B. The direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. RadHard TM
LOGIC SYMBOL
O E1 (48) O E2 (25) DIR1 (1) G1 2EN1 (BA) 2EN2 (AB) 1EN1 (BA) 1EN2 (AB) G2 11 12 (24) DIR2
1A1 1A2 1A3
(47) (46) (44)
(2) (3) (5) (6) (8)
1B1 1B2 1B3 1B4
(43) 1A4 (41) 1A5 (40) 1A6 (38) 1A7 (37) 1A8 (36) 2A1 2A2 2A3 (35) (33)
21 22
1B5 (9) 1B6 (11) 1B7 (12) 1B8 (13) 2B1 (14) 2B2 (16) 2B3 (17) 2B4 (19) 2B5 (20) 2B6 (22) 2B7 (23) 2B8
(32) 2A4 (30) 2A5 (29) 2A6 (27) 2A7 (26) 2A8
PIN DESCRIPTION
Pin Names OE x DIRx xAx xBx Description Output Enable Input (Active Low) Direction Control Inputs Side A Inputs or 3-State Outputs (3.3V Port) Side B Inputs or 3-State Outputs (5V Port)
FUNCTION TABLE
ENABLE OE x L L H DIRECTION DIRx L H X OPERATION B Data To A Bus A Data To B Bus Isolation
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PINOUTS POWER TABLE1
Port B 5 Volts Port A 3.3 Volts 5 Volts 3.3 Volts V SS 3.3V or 5V OPERATION Voltage Translator Non Translating Non Translating Cold Spare Port B Cold Spare
48-Lead Flatpack Top View
DIR1 1B1 1B2 V SS 1B3 1B4 VDD1 1B5 1B6 V SS 1B7 1B8 2B1 2B2 V SS 2B3 2B4 VDD1 2B5 2B6 V SS 2B7 2B8 DIR2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OE1 1A1 1A2 V SS 1A3 1A4 VDD2 1A5 1A6 V SS 1A7 1A8 2A1 2A2 V SS 2A3 2A4 VDD2 2A5 2A6 V SS 2A7 2A8 O E2
5 Volts 3.3 Volts V SS V SS NOTE:
1. V DD2 cannot be tied to V SS while power is applied to VD D 1.
Control signals DIRx and OEx are 5 volt tolerant inputs. When V DD2 is at 3.3 volts, either 3.3 or 5 volt CMOS logic levels can be applied to all control inputs. For proper operation connect power to all VDD and ground all V SS pins (i.e., no floating V DD or V SS input pins). Tie unused inputs to VSS . If VDD1 and V DD2 are not powered up together, then V DD2 should be powered up first for proper control of OE and DIR. Until V DD2 reaches 2.75V + 5%, control of the outputs by OE and DIR cannot be guaranteed. During operation of the part, after power up, insure VDD1 > V DD2 . Tie unused inputs to V SS .
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LOGIC DIAGRAM
DIR1
(1) (48) O E1
DIR2
(24) (25) OE 2
1A1
(47) (2) 1B1
2A1
(36) (13) 2B1
1A2
(46) (3) 1B2
2A2
(35) (14) 2B2
1A3
(44) (5) 1B3
2A3
(33) (16) 2B3
3.3V PORT
3.3V PORT
1A4
(43)
2A4
(32) (17) (30) (19) 2B5 2B4
5 V PORT
(6) (41) (8) 1A6 (40) (9) 1A7 (38) (11) 1A8 (37) (12)
1B4
1A5
2A5
1B5 2A6 1B6 2A7 1B7 2A8 1B8 (26) (27) (29)
(20)
2B6
(22)
2B7
(23)
2B8
3
5 V PORT
RADIATION HARDNESS SPECIFICATIONS PARAMETER Total Dose SEL Latchup Neutron Fluence 2
1
LIMIT 1.0E5 >120 1.0E14
UNITS rad(Si) MeV-cm2 /mg n/cm 2
Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS 1 SYMBOL V I/O V DD1 V DD2 TSTG TJ J C II PD PARAMETER Voltage any pin Supply voltage Supply voltage Storage Temperature range Maximum junction temperature Thermal resistance junction to case DC input current Maximum power dissipation LIMIT (Mil only) -.3 to V DD1 +.3 -0.3 to 6.0 -0.3 to 6.0 -65 to +150 +175 20 10 1 UNITS V V V C C C/W mA W
Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.
DUAL SUPPLY OPERATING CONDITIONS SYMBOL V DD1 V DD2 V IN TC PARAMETER Supply voltage Supply voltage Input voltage any pin Temperature range LIMIT 3.0 to 3.6 or 4.5 to 5.5 3.0 to 3.6 or 4.5 to 5.5 0 to VDD1 -55 to + 125 UNITS V V V C
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DC ELECTRICAL CHARACTERISTICS 1 ( -55C < TC < +125C) (T C = -55 C to +125C for "C" screening and -40C to +125 C for "W" screening) SYMBOL VT + V TV H1 V H2 IIN PARAMETER Schmitt Trigger, positive going threshold2 CONDITION V DD from 3.00 to 5.5 .3VDD 0.6 0.4 -1 3 MIN MAX .7VDD UNIT V V V V A
Schmitt Trigger, negative going threshold2 V DD from 3.00 to 5.5 Schmitt Trigger range of hysteresis10 Schmitt Trigger range of hysteresis10 Input leakage current10 V DD from 4.5 to 5.5 V DD from 3.00 to 3.6 V DD from 3.6 to 5.5 V IN = V DD or VSS
I OZ
Three-state output leakage current10
V DD from 3.6 to 5.5 V IN = V DD or VSS
-1
3
A
ICS
Cold sparing leakage current 3
V IN = 5.5 V DD = V SS
-1
5
A
IOS1
Short-circuit output current 6, 11
V O = V DD or VSS V DD from 4.5 to 5.5
-200
200
mA
IOS2
Short-circuit output current 6, 11
V O = V DD or VSS V DD from 3.00 to 3.6
-100
100
mA
VOL1
Low-level output voltage4, 10
I OL= 8mA I OL= 100A V DD = 4.5
0.4 0.2
V
VOL2
Low-level output voltage4, 10
I OL= 8mA I OL= 100A V DD = 3.00
0.5 0.2
V
V OH1
High-level output voltage4, 10
I OH= -8mA I OH= -100A V DD = 4.5
V DD - 0.7 VDD - 0.2 V DD - 0.9 VDD - 0.2
V
V OH2
High-level output voltage4, 10
I OH= -8mA I OH= -100A V DD = 3.00
V
5
Ptotal1
Power dissipation 5,7, 8
CL = 50pF V DD from 4.5 to 5.5
2.0
mW/ MHz mW/ MHz
Ptotal2
Power dissipation 5, 7, 8
CL = 50pF V DD from 3.00 to 3.6
1.5
I DD
Standby Supply Current VDD1 or VDD2
V IN = V DD or VSS V DD = 5.5
Pre-Rad 25oC Pre-Rad -55o C to +125oC Post-Rad 25oC CIN Input capacitance 9
OE=V DD OE=V DD OE=V DD = 1MHz @ 0V V DD from 3.00 to 5.5
10 100 500 15
A A A pF
COUT
Output capacitance9
= 1MHz @ 0V V DD from 3.00 to 5.5
15
pF
Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = V IH (min) + 20%, - 0%; V IL = V IL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within th e above specified range, but are guaranteed to V IH (min) and VIL (max). 3. All combinations of OEx and DIRx 4. Per MIL-PRF-38535, for current density 5.0E5 amps/cm 2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF-MHz. 5. Guaranteed by characterization. 6. Not more than one output may be shorted at a time for maximum duration of one second. 7. Power does not include power contribution of any CMOS output sink current. 8. Power dissipation specified per switching output. 9.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 10 .Guaranteed; tested on a sample of pins per device. 11. Supplied as a design limit, but not guaranteed or tested. .
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AC ELECTRICAL CHARACTERISTICS 1 (Port B = 5 Volt, Port A = 3.3 Volt)
(V DD1 = 5V 10%; V DD2 = 3.00V to 3.6V, -55C < TC < +125 C) (T C = -55 C to +125 C for "C" screening and -40 to +125 for "W" screening C C
SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL 2 tPZH2 tPLZ 2 tPHZ2
PARAMETER Propagation delay Data to Bus Propagation delay Data to Bus Output enable time OEx to Bus Output enable time OEx to Bus Output disable time OEx to Bus high impedance Output disable time OEx to Bus high impedance Output enable time DIRx to Bus Output enable time DIRx to Bus Output disable time DIRx to Bus high impedance Output disable time DIRx to Bus high impedance
MINIMUM 1 1 1 1 1 1 1 1 1 1
MAXIMUM 20 20 18 18 20 20 18 18 20 20
UNIT ns ns ns ns ns ns ns ns ns ns
Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested.
Propagation Delay Input Output
tPLH tPHL
V DD V DD /2 0V V OH V DD /2 V OL
Enable Disable Times Control Input 5V Output Normally Low 5V Output Normally High
tPZL V DD/2-0.2 tPZH V DD /2+0.2 tPZL tPLZ .2VDD + .2V tPHZ .8VDD - .2V tPLZ VDD /2-0.2 tPZH VDD /2+0.2 .2V DD + .2V tPHZ .7V DD - .2V V DD V DD /2 0V V DD /2 .2V DD .8V DD V DD /2
3.3V Output Normally Low 3.3V Output Normally High
VDD /2 .2VDD .7VDD VDD /2
7
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AC ELECTRICAL CHARACTERISTICS 1 (Port A = Port B, 5 Volt Operation) (VDD1 = 5V 10%; V DD2 = 5.0V +10%, -55C < T C < +125C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL 2 tPZH2 tPLZ 2 tPHZ2 PARAMETER Propagation delay Data to Bus Propagation delay Data to Bus Output enable time OEx to Bus Output enable time OEx to Bus Output disable time OEx to Bus high impedance Output disable time OEx to Bus high impedance Output enable time DIRx to Bus Output enable time DIRx to Bus Output disable time DIRx to Bus high impedance Output disable time DIRx to Bus high impedance MINIMUM 1 1 1 1 1 1 1 1 1 1 MAXIMUM 15 15 12 12 15 15 12 12 15 15 UNIT ns ns ns ns ns ns ns ns ns ns
Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested
Propagation Delay Input Output
tPLH tPHL
V DD V DD/2 0V V OH V DD/2 V OL
Enable Disable Times Control Input 5V Output Normally Low 5V Output Normally High
tPZL V DD/2-0.2 tPZH V DD/2+0.2 tPLZ .2VDD + .2V tPHZ .8V DD - .2V V DD V DD/2 0V V DD/2 .2V DD .8V DD V DD/2
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AC ELECTRICAL CHARACTERISTICS 1 (Port A = Port B, 3.3 Volt Operation) (VDD1 = 3.00V to 3.6V; V DD2 = 3.00V to 3.6V, -55C < TC < +125C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL 2 tPZH2 tPLZ 2 tPHZ2 PARAMETER Propagation delay Data to Bus Propagation delay Data to Bus Output enable time OEx to Bus Output enable time OEx to Bus Output disable time OEx to Bus high impedance Output disable time OEx to Bus high impedance Output enable time DIRx to Bus Output enable time DIRx to Bus Output disable time DIRx to Bus high impedance Output disable time DIRx to Bus high impedance MINIMUM 1 1 1 1 1 1 1 1 1 1 MAXIMUM 20 20 18 18 20 20 18 18 20 20 UNIT ns ns ns ns ns ns ns ns ns ns
Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019 . 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested.
Propagation Delay Input Output
tPLH tPHL
V DD V DD /2 0V V OH V DD /2 V OL
Enable Disable Times Control Input 3.3V Output Normally Low 3.3V Output Normally High
tPZL V DD/2-0.2 tPZH V DD /2+0.2 tPLZ .2VDD + .2V tPHZ .7VDD - .2V V DD V DD /2 0V V DD /2 .2V DD .7VDD V DD /2
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PACKAGE
5
6
4
6
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003.
Figure 1. 48-Lead Flatpack
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ORDERING INFORMATION
UT54ACS164245S: SMD
5962
R 98580 **
*
*
*
Lead Finish: (C) = Gold
Case Outline: (X) = 48 lead BB FP (Gold only)
Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 16-bit MultiPurpose Transceiver (3.13V - 5.5V) (02) = 16-bit MultiPurpose Transceiver (3.0V - 5.5V) (03) = Extended Industrial Temp (-40 oC to +125oC) Drawing Number: 98580 Total Dose: (R) = 1E5 rad(Si)
Federal Stock Class Designator: No options
Notes: 1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
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UT54ACS164245S
UT54 *** ****** * * *
Lead Finish: (C) = Gold
Screening: (C) (P) = = Mil Temp Prototype Extended Industrial Temp (-40 oC to +125 oC)
(W) =
Package Type: (U) = 48-lead BB FP (Gold only)
Part Number: (164245S) = 16-bit MultiPurpose Transceiver
I/O Type: (ACS)= CMOS compatible I/O Level
UTMC Core Part Number
Notes: 1. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation n either tested nor guaranteed. 2. Prototype flow per UTMC Manufacturing Flows Document Tested at 25C only. Lead finish is gold only. 3. Extended Industrial Temperature Range Flow per UTMC Manufacturing Flows Document. Devices are tested at -40oC, room temp, and +125 oC. Radiation is neither tested nor guaranteed
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